This invention relates to signal processing circuits for limiting the voltage level of the signal induced, for example, across a signal source coil, within a range between an upper and lower limits.
FIG. 3 is a circuit diagram showing a conventional signal processing circuit provided with a voltage limiter circuit. The signal voltage generated across the signal source coil 1 by means of the electromagnetic induction is applied across a signal input terminal 8 and a reference input terminal 9 through a voltage limiter resistor 3. A signal processing circuit 6 implemented as an IC (integrated circuit) includes: a reference voltage generator circuit 2 for determining the voltage of the reference input terminal 9; a voltage limiter circuit 5 for limiting the signal voltage; a comparator 4 for comparing the signal with a predetermined reference level and outputting the result of comparison to a signal output terminal 10; and a Zener diode 7 coupled across a voltage source terminal 11 and a grounded terminal 12 for limiting the source voltage.
The voltage limiter circuit 5 consists of transistors 54 and 55 and resistors 51, 52 and 53 The reference voltage generator circuit 2 consists of an amplifier 2a and resistors 2b and 2c. The voltage source 100 coupled to the voltage source terminal 11 has a source impedance 100a.
Next, the operation of the voltage limiter circuit 5 for limiting the signal voltage is described. The voltage induced across the signal source coil 1 is applied across the signal input terminal 8 and the reference input terminal 9 through the voltage limiter resistor 3. When the voltage at the signal input terminal 8 relative to the voltage at the reference input terminal 9 exceeds a predetermined upper limit, the emitter-base voltage of the PNP transistor 55 is biased in the forward direction, and the PNP transistor 55 is turned on. As a result, the current flows from the signal input terminal 8 to the ground through the PNP transistor 55 and the grounded terminal 12, thereby limiting the voltage at the signal input terminal 8 below the predetermined upper limit.
When, on the other hand, the signal voltage falls below a predetermined lower limit, the emitter-base voltage of the NPN transistor 54 is biased in the forward direction, and the NPN transistor 54 is turned on. As a result, the current flows from the voltage source 100 to the signal input terminal 8 through the voltage source terminal 11 and the NPN transistor 54, and thereby maintains the voltage at the signal input terminal 8 above the predetermined lower limit.
The upper and the lower limits of the signal voltage are determined by the resistances R.sub.1, R.sub.2 and R.sub.3 of the resistors 51, 52 and 53. Namely, the base voltage of the PNP transistor 55 is determined by the voltage V.sub.D at the point D between the resistors 51 and 52, which is given by: EQU V.sub.D =V.sub.cc .multidot.(R.sub.2 +R.sub.3)/(R.sub.1 +R.sub.2 +R.sub.3)
where V.sub.CC is the source voltage at the voltage source terminal 11. Thus, if the voltage at the signal. input terminal 8 exceeds V.sub.D +V.sub.f, where V.sub.f is the forward voltage across the emitter band the base of the PNP transistor 55, the PNP transistor 55 is turned on and thereby limits the signal voltage below the upper limit V.sub.D +V.sub.f.
On the other hand, the base voltage of the NPN transistor 54 is determined by the voltage V.sub.E at the point E between the resistors 52 and 53, which is given by: EQU V.sub.E =V.sub.cc .multidot.R.sub.3 /(R.sub.1 +R.sub.2 +R.sub.3)
where V.sub.cc is the source voltage at the voltage source terminal 11. Thus, if the voltage at the signal input terminal 8 falls below V.sub.E .about.-V.sub.f, where V.sub.f is the forward voltage across the base and emitter of the NPN transistor 54, the NPN transistor 54 is turned on and thereby maintains the signal voltage above the lower limit V.sub.E -V.sub.f.
The above conventional signal processing circuit, however, has the following disadvantage. When the signal voltage falls below the lower limit, the current is supplied from the voltage source 100 through the source impedance 100a and the NPN transistor 54, and the voltage at the signal input terminal 8 is maintained above the lower limit V.sub.E -V.sub.f. Thus, especially in the case where the value of the source impedance 100a is large, the source voltage at the voltage source terminal 11 varies greatly due to the operation of the voltage limiter circuit 5.
Further, assume that the resistance value of the source impedance 100a is not negligible compared with the resistance values of the resistors 2b and 2c. Then, when the current flows through the source impedance 100a due to the operation of the voltage limiter circuit 5, the voltage at the positive terminal of the amplifier 2a varies. As a result, the reference voltage provided by the reference voltage generator circuit 2 also varies. Furthermore, when the response speed of the reference voltage generator circuit 2 is slow, the operation thereof cannot follow that of the voltage limiter circuit 5. This may also cause a variation of the reference voltage provided by the reference voltage generator circuit 2.